Memory systems in an integrated circuit (IC) device may include built-in self-test (BIST) circuitry. The term “built-in” means that the circuitry is fabricated on the same IC chip as the memory array to be tested and forms an integral part of the overall memory system. Such BIST circuitry can be used to test a memory array of a newly manufactured IC device.
As illustrated in FIG. 1, a typical integrated memory system 10 having BIST circuitry includes a memory subsystem 12, sequential control logic 14, write data decoding logic 16, memory control signal decoding logic 18, address counter logic 20, address comparison logic 22, and test data comparison logic 24. The memory array to be tested is internal to memory subsystem 12 and not separately shown in FIG. 1 for purposes of clarity. The BIST circuitry, in accordance with an algorithm, commonly first writes test data to all of the memory locations in the memory array in the sequence of their addresses, and then reads back those memory locations in the same sequence, comparing the data that is read back with expected data. If the data that is read back does not match the expected data, an error condition is flagged.
In normal operation, i.e., when the BIST circuitry is not being used to test the memory array in memory subsystem 12, memory subsystem 12 can perform read operations and write operations in response to data and addresses received from a processor (not shown) or other system external to memory system 10. In response to such an external system initiating a write operation, memory subsystem 12 writes the data that the external device presents at a normal data input 26 to a memory location corresponding to an address that the external system presents at a normal address input 28. In response to such an external system initiating a read operation, memory subsystem 12 reads data from a memory location corresponding to an address that the external device presents at normal address input 28. Although not separately shown in FIG. 1 for purposes of clarity, memory subsystem 12 includes an internal data output register that registers or temporarily stores each data word as it is read from the memory array. In normal operation, i.e., when the BIST circuitry is not being used to test the memory array in memory subsystem 12, the output of this data output register is presented to the data output 30 of memory subsystem 12.
Memory system 10 can be switched or selected to operate in either the normal operational mode described in the preceding paragraph or the BIST mode. A data input multiplexer (not shown) internal to memory subsystem 12 selects normal data input 26 in the normal operational (i.e., non-BIST) mode or a test data input 27 in BIST mode. An address input multiplexer (not shown) internal to memory subsystem 12 selects normal address input 28 in normal operational (i.e., non-BIST) mode or a test address input 29 in BIST mode. When BIST mode is selected, memory system 10 operates as follows.
A clock signal (“CLK”) maintains the sequential elements of integrated memory system 10 in synchronization with each other. Sequential control logic 14 is similar to a state machine in that it cycles through a sequence of states. State flip-flops 30 in sequential control logic 14 maintain or store the current state. Next state decoding logic 32 determines the next state in the sequence of states in response to the current state and in response to a pass-fail signal 34 and a maximum address signal 36. As sequential control logic 14 enters the next state in the sequence of states, it outputs state information signals 38. Write data decoding logic 16 decodes some of state information signals 38 to produce expected data and test data. Memory subsystem 12 receives the test data from write data decoding logic 16 on the test data input 27. Memory control signal decoding logic 18 decodes some of state information signals 38 to produce memory control signals 39 generally of the type commonly referred to as enable signals. On each clock cycle, memory control signals 39 indicate whether a write operation is to be performed, a read operation is to be performed, or neither a read nor a write operation is to be performed. Memory subsystem 12 receives test data at test data input 27. Memory subsystem 12 also receives a test address, which can be referred to as the “current address,” from address counter logic 20 at test address input 29. Although not separately shown in FIG. 1 for purposes of clarity, the test data and current address are temporarily stored or registered in a data register and an address register, respectively, internal to memory subsystem 12. This address register provides an address, which can be referred to as the “last address,” directly to the memory array. The last address, i.e., the contents of the address register, is also provided to address counter logic 20. Address counter logic 20 essentially comprises an adder that, under some conditions, adds one to the last address to produce the current address. Under some conditions, address counter logic 20 may add a number other than one to the last address or may subtract a number from the last address.
Test data comparison logic 24 receives the expected data from write data decoding logic 16. In response to some of state information signals 38, address counter logic 20 generally does one of the following on the next clock cycle, depending on the state: increment the current address by one; hold the current address; and reset the address to zero (or some other base address in the memory address space).
Address comparison logic 22 compares the current address to a maximum address (“MAX_ADDR”) that represents the ending address of the sequence of addresses to be tested. Memory locations spanning addresses from the base address to the maximum address are tested. If the current address matches the maximum address, address comparison logic 22 provides a maximum address signal (“AT_MAX”) to next state decoding logic 32 of sequential control logic 14. Thus, if sequential control logic 14 determines that the write or read operations have reached the maximum address, sequential control logic 14 can cause the write or read operations to stop by generating state information signals 38 in which a stop or “hold” condition is encoded. Memory control signal decoding logic 18 decodes such state information signals 38 in a manner that adjusts memory control signals 39 to inhibit the memory array from performing a next write or read operation. Thus, when the BIST circuitry is writing test data, the addresses to which the test data values are written are generally incremented by one on each successive clock cycle until the maximum address is reached.
When the BIST circuitry is reading back memory locations, the data read from each memory location is registered in the above-referenced data output register that is internal to memory subsystem 12. In BIST mode, memory subsystem 12 provides the contents of this register at a data output 40. Data comparison logic 24 compares the value read back from a memory location with an expected data value. If the value that is read back matches the expected value, data comparison logic 24 sets the value of a pass-fail signal 42 to indicate that the test of that memory location passed. If the value that is read back does not match the expected value, data comparison logic 24 sets the value of pass-fail signal 42 to indicate that the test of that memory location failed. Although not shown for purposes of clarity, memory system 10 includes additional circuitry that outputs information identifying addresses at which the test failed to an external system (e.g., not on the same IC chip as memory system 10). If sequential control logic 14 determines that such a test failure has occurred, sequential control logic 14 can cause the read operations to stop by generating state information signals 38 in which a “hold” condition is encoded. Memory control signal decoding logic 18 decodes such state information signals 38 in a manner that adjusts memory control signals 39 to inhibit the memory array from performing a next read operation. Thus, when the BIST circuitry is reading test data, the addresses from which the test data values are read are generally incremented by one on each successive clock cycle until either a failure is detected or the maximum address is reached.
It is desirable to test the memory array of memory subsystem 12 at the highest speed possible. However, the speed at which the memory array can be tested is limited by the propagation delays through the combinational logic, including write data decoding logic 16, memory control signal decoding logic 18, address counter logic 20, address comparison logic 22, test data comparison logic 24, and next state decoding logic 32.